US 12,282,318 B2
Semiconductor wafer cooling
Yung-Yao Lee, Zhubei (TW); Cheng-Kang Hu, Kaohsiung (TW); Jui-Chun Peng, Hsinchu (TW); and Hsu-Shui Liu, Pingjhen (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 31, 2023, as Appl. No. 18/362,037.
Application 18/362,037 is a continuation of application No. 17/301,322, filed on Mar. 31, 2021, granted, now 11,768,484.
Prior Publication US 2023/0384776 A1, Nov. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G05B 19/418 (2006.01); G06T 7/13 (2017.01); G06T 7/62 (2017.01)
CPC G05B 19/41875 (2013.01) [G06T 7/13 (2017.01); G06T 7/62 (2017.01); G05B 2219/45027 (2013.01); G05B 2219/45028 (2013.01); G05B 2219/45031 (2013.01); G05B 2219/45183 (2013.01); G06T 2207/30148 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving, by a cooling controller, wafer information associated with a wafer from one or more sensors;
determining, by the cooling controller and based on the wafer information, a center point of the wafer,
wherein the center point of the wafer is based on a plurality of edge points for the wafer;
determining, by the cooling controller and based on the center point, a plurality of field edge points for the wafer,
wherein a quantity of the plurality of edge points is different from a quantity of the plurality of field edge points;
determining, by the cooling controller, a pattern mask area based on the plurality of field edge points;
determining, by the cooling controller, a cooling time for the wafer based on the pattern mask area and exposure process information; and
causing, by the cooling controller, a cooling plate to cool the wafer for a time duration equal to the cooling time.