US 12,282,317 B2
Wafer defect test apparatus, wafer defect test system, wafer test method and fabrication method of a wafer
Sung Hee Lee, Osan-si (KR); Jae Yoon Kim, Seoul (KR); Jung Hwan Moon, Seoul (KR); Jung Hoon Bak, Suwon-si (KR); Kyu-Baik Chang, Seoul (KR); Jae Hoon Jeong, Hwaseong-si (KR); and Min Kyoung Joo, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Feb. 25, 2022, as Appl. No. 17/680,958.
Claims priority of application No. 10-2021-0110621 (KR), filed on Aug. 23, 2021.
Prior Publication US 2023/0055058 A1, Feb. 23, 2023
Int. Cl. G05B 19/418 (2006.01); G06N 5/02 (2023.01)
CPC G05B 19/41875 (2013.01) [G06N 5/02 (2013.01); G05B 2219/32368 (2013.01); G05B 2219/45031 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A wafer defect test apparatus, comprising:
a wafer variable generator configured to:
receive a first structural measurement data and a first process condition data of a first wafer, and a second structural measurement data and a second process condition data of a second wafer;
generate a first process variable and a second process variable based on the first structural measurement data and the first process condition data; and
generate a third process variable and a fourth process variable based on the second structural measurement data and the second process condition data;
an abnormal wafer index generating circuit configured to:
generate a first wafer vector of the first process variable and the second process variable;
generate a second wafer vector of the third process variable and the fourth process variable;
calculate a first Euclidean distance between the first wafer vector and the second wafer vector;
calculate a first Cosine distance between the first wafer vector and the second wafer vector; and
generate a first abnormal wafer index of the first wafer based on a product of the first Euclidean distance and the first Cosine distance;
a prediction model generating circuit configured to:
receive a first characteristic variable that is a test result of the first wafer;
generate a wafer defect prediction model through a regression based on the first process variable, the second process variable, the first characteristic variable, and the first abnormal wafer index; and
an abnormal wafer detector configured to test whether the first wafer is defective based on the wafer defect prediction model and the first abnormal wafer index.