US 12,282,255 B2
Silver patterning and interconnect processes
You-Hua Chou, Hsinchu (TW); and Kuosheng Chuang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 10, 2024, as Appl. No. 18/739,140.
Application 18/739,140 is a division of application No. 18/327,785, filed on Jun. 1, 2023, granted, now 12,025,914.
Application 18/327,785 is a division of application No. 16/803,885, filed on Feb. 27, 2020, granted, now 11,681,225, issued on Jun. 20, 2023.
Prior Publication US 2024/0329533 A1, Oct. 3, 2024
Int. Cl. H01L 21/00 (2006.01); G03F 7/06 (2006.01); H01L 21/033 (2006.01)
CPC G03F 7/06 (2013.01) [H01L 21/0332 (2013.01); H01L 21/0337 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor device, comprising:
depositing a hard mask layer over a substrate;
depositing a silver precursor layer over the hard mask layer;
exposing portions of the silver precursor layer to a radiation, the radiation causing reduction of silver ions in the irradiated portions of the silver precursor layer;
removing non-irradiated portions of the silver precursor layer, resulting in a plurality of silver seed structures;
forming a plurality of patterned silver structures by depositing silver on top and sidewall surfaces of the plurality of silver seed structures; and
etching the hard mask layer and the substrate using the plurality of patterned silver structures as an etch mask.