US 12,282,249 B2
Full-chip cell critical dimension correction method and method of manufacturing mask using the same
Kisung Kim, Seoul (KR); Donggon Woo, Yongin-si (KR); Heejun Lee, Seoul (KR); and Dongho Kim, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jul. 7, 2022, as Appl. No. 17/859,288.
Claims priority of application No. 10-2021-0169336 (KR), filed on Nov. 30, 2021.
Prior Publication US 2023/0168576 A1, Jun. 1, 2023
Int. Cl. G03F 1/36 (2012.01); G03F 1/70 (2012.01); G03F 7/00 (2006.01)
CPC G03F 1/36 (2013.01) [G03F 1/70 (2013.01); G03F 7/705 (2013.01); G03F 7/70508 (2013.01); G03F 7/70625 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A full-chip cell critical dimension (CD) correction method comprising:
receiving a database (DB) about a full-shot;
analyzing a hierarchy of the DB;
generating a density map of a full-chip by using the DB;
converting the density map into a retarget rule table, the converting including mapping the density map using a density rule;
reconfiguring cell blocks of the full-chip into an optical proximity correction (OPC) target cell layout;
applying a first bias to the OPC target cell layout based on the retarget rule table; and
generating an optical proximity corrected (OPC'ed) layout for the full-chip by performing hierarchical OPC.