US 12,282,241 B2
Display panel and display device
Wenli Fan, Beijing (CN); Tao Fang, Beijing (CN); Meiying Li, Beijing (CN); Zecun Zeng, Beijing (CN); Liqing Yao, Beijing (CN); Xin Fang, Beijing (CN); Shanshan Xu, Beijing (CN); Wenchao Wang, Beijing (CN); Sang Jin Park, Beijing (CN); Baoqiang Wang, Beijing (CN); and Kai Diao, Beijing (CN)
Assigned to Fuzhou BOE Optoelectronics Technology Co., Ltd., Fujian (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 18/564,104
Filed by Fuzhou BOE Optoelectronics Technology Co., Ltd., Fujian (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed May 28, 2021, PCT No. PCT/CN2021/097001
§ 371(c)(1), (2) Date Nov. 27, 2023,
PCT Pub. No. WO2022/246859, PCT Pub. Date Dec. 1, 2022.
Prior Publication US 2024/0248360 A1, Jul. 25, 2024
Int. Cl. G02F 1/1368 (2006.01); G02F 1/1343 (2006.01); G02F 1/1362 (2006.01)
CPC G02F 1/1368 (2013.01) [G02F 1/134372 (2021.01); G02F 1/136209 (2013.01); G02F 1/136286 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A display panel, wherein the display panel comprises: a plurality of pixels arranged in an array; each of the pixels comprises a plurality of sub-pixels; the plurality of pixels arranged in the array comprise a plurality of pixel rows; each of the pixel row comprises a plurality of sub-pixels arranged along a first direction, and the plurality of pixel rows extend along a second direction; the first direction and the second direction intersect;
the display panel specifically comprises: a first array substrate and a first opposite substrate which are disposed opposite to each other, and a first liquid crystal layer which is located between the first array substrate and the first opposite substrate; the first array substrate comprises a plurality of first driving transistors arranged in an array; at least one pixel is spaced between two adjacent first driving transistors in the first direction; the first opposite substrate comprises a plurality of light shielding parts corresponding to the first driving transistors one-to-one; and an orthographic projection of each of the light shielding parts on a plane where the first array substrate is located only covers an orthographic projection of a respective one of the first driving transistors on the plane where the first array substrate is located,
wherein a shape of an orthographic projection of a light shielding part on the first array substrate is a rectangle with a chamfering angle, and a length of the rectangle in the first direction is greater than or equal to 30 microns and less than or equal to 180 microns, and a width of the rectangle in the second direction is greater than or equal to 30 microns and less than or equal to 180 microns.