US 12,282,240 B2
Display device and electronic device
Susumu Kawashima, Kanagawa (JP); and Naoto Kusumoto, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Sep. 15, 2023, as Appl. No. 18/368,632.
Application 18/368,632 is a continuation of application No. 17/963,243, filed on Oct. 11, 2022, granted, now 11,762,250.
Application 17/963,243 is a continuation of application No. 17/047,149, granted, now 11,513,405, issued on Nov. 29, 2022, previously published as PCT/IB2019/053250, filed on Apr. 19, 2019.
Claims priority of application No. 2018-085668 (JP), filed on Apr. 26, 2018.
Prior Publication US 2024/0004248 A1, Jan. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G09G 3/30 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); H01L 27/12 (2006.01); G09G 3/3225 (2016.01); G09G 3/3266 (2016.01); G09G 3/36 (2006.01); H04N 23/57 (2023.01); H10K 59/121 (2023.01)
CPC G02F 1/13624 (2013.01) [G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); H01L 27/1225 (2013.01); H01L 27/1255 (2013.01); G09G 3/3225 (2013.01); G09G 3/3266 (2013.01); G09G 3/3677 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0465 (2013.01); G09G 2300/0852 (2013.01); G09G 2310/0286 (2013.01); G09G 2320/0233 (2013.01); G09G 2330/021 (2013.01); H04N 23/57 (2023.01); H10K 59/1213 (2023.02); H10K 59/1216 (2023.02)] 8 Claims
OG exemplary drawing
 
1. A display device comprising:
a source driver;
a first circuit electrically connected to the source driver;
a second circuit electrically connected to the first circuit; and
a third circuit electrically connected to the first circuit,
wherein the first circuit comprises a first transistor, a second transistor, and a capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to the source driver,
wherein the other of the source and the drain of the first transistor is electrically connected to a first electrode of the capacitor,
wherein one of a source and a drain of the second transistor is electrically connected to a second electrode of the capacitor,
wherein the second circuit comprises a first display element and a third transistor electrically connected to the first display element,
wherein the third circuit comprises a second display element and a fourth transistor electrically connected to the second display element, and
wherein the third transistor and the fourth transistor are electrically connected to the first transistor.