US 12,282,058 B2
Integrated circuit pad failure detection
Eyal Fayneh, Givatayim (IL); Shai Cohen, Haifa (IL); Evelyn Landman, Haifa (IL); Yahel David, Kibbutz Gazit (IL); and Inbar Weintrob, Givat-Ada (IL)
Assigned to PROTEANTECS LTD., Haifa (IL)
Filed by PROTEANTECS LTD., Haifa (IL)
Filed on Jul. 18, 2022, as Appl. No. 17/866,615.
Application 17/866,615 is a continuation in part of application No. 16/765,997, granted, now 11,391,771, previously published as PCT/IL2018/051267, filed on Nov. 22, 2018.
Claims priority of provisional application 62/590,308, filed on Nov. 23, 2017.
Prior Publication US 2022/0349935 A1, Nov. 3, 2022
Int. Cl. G01R 31/28 (2006.01); G04F 10/00 (2006.01)
CPC G01R 31/2879 (2013.01) [G01R 31/2881 (2013.01); G04F 10/005 (2013.01)] 22 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) comprising:
a time-to-digital converter (TDC) configured to measure an input-to-output delay of an I/O buffer of a pad the IC, the measured delay reflecting a connection impedance of the pad; and
a circuit configured to determine electrical connection integrity of the pad, based on the measurement by the TDC.