US 11,963,343 B2
Semiconductor device and operation method thereof
Hitoshi Kunitake, Kanagawa (JP); Ryunosuke Honda, Kanagawa (JP); and Tomoaki Atsumi, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Aug. 22, 2022, as Appl. No. 17/892,190.
Application 17/892,190 is a continuation of application No. 16/959,771, granted, now 11,430,791, previously published as PCT/IB2019/050207, filed on Jan. 11, 2019.
Claims priority of application No. 2018-007209 (JP), filed on Jan. 19, 2018.
Prior Publication US 2023/0127474 A1, Apr. 27, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/4074 (2006.01); G11C 11/405 (2006.01); H01L 29/66 (2006.01); H10B 12/00 (2023.01)
CPC H10B 12/00 (2023.02) [G11C 11/405 (2013.01); G11C 11/4074 (2013.01); H01L 29/66083 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A method for operating a semiconductor device comprising a first transistor, a first capacitor, a first output terminal, a first switch, and a second switch,
wherein a gate and a source of the first transistor are electrically connected to each other,
wherein a first terminal of the first capacitor and the first output terminal are electrically connected to a back gate of the first transistor,
wherein a second terminal of the first capacitor is electrically connected to the source,
wherein the first switch controls input of a first voltage to the back gate,
wherein a second voltage is input to a drain of the first transistor, and
wherein the second switch controls input of a third voltage to the source,
the method comprising:
turning on the first switch and the second switch in a first period;
turning off the second switch in a second period after the first period;
turning off the first switch in a third period after the second period; and
turning on the second switch in a fourth period after the third period.