US 11,962,926 B2
Image sensor with configurable pixel circuit and method
Yingyun Zha, Regensdorf (CH); Jian Deng, Zurich (CH); and Roger Mark Bostock, Munsingen (CH)
Assigned to Alpsentek GmbH, Zurich (CH)
Appl. No. 18/002,775
Filed by Beijing RuisiZhixin Technology Co., Ltd., Beijing (CN); and Alpsentek GmbH, Zurich (CH)
PCT Filed Aug. 4, 2021, PCT No. PCT/EP2021/071773
§ 371(c)(1), (2) Date Dec. 21, 2022,
PCT Pub. No. WO2022/033936, PCT Pub. Date Feb. 17, 2022.
Claims priority of application No. 20191068 (EP), filed on Aug. 14, 2020.
Prior Publication US 2023/0247325 A1, Aug. 3, 2023
Int. Cl. H04N 25/77 (2023.01); H01L 27/146 (2006.01); H04N 25/571 (2023.01); H04N 25/766 (2023.01)
CPC H04N 25/77 (2023.01) [H01L 27/14612 (2013.01); H04N 25/573 (2023.01); H04N 25/766 (2023.01)] 22 Claims
OG exemplary drawing
 
1. An image sensor comprising a plurality of pixel circuits each comprising:
a photodiode connected between ground and a floating diffusion (FD) node,
a reset transistor (MRST) configured to be connected between a first voltage supply and the floating diffusion (FD) node,
a source follower transistor (MSF), wherein a drain of the source follower transistor (MSF) is connected to a second voltage supply, a gate of the source follower transistor (MSF) is connected to the floating diffusion (FD) node and a source of the source follower transistor (MSF) is connected to a row select transistor (MSEL), and
the row select transistor (MSEL) is connected between the source of the source follower transistor (MSF) and a common column output,
wherein each pixel circuit is configured to provide an output signal corresponding to a light incident on the photodiode; and
wherein, to configure each pixel circuit to selectively output a linear integration signal or a logarithmic signal, each pixel circuit further comprises:
a first additional bias transistor (MVB) connected between the second voltage supply and the drain of the source follower transistor (MSF), and
a second additional transistor (MS2) configured to connect a drain of the bias transistor (MVB) to a drain of the reset transistor (MRST), and
a third additional transistor (MS3) configured to connect the reset transistor (MRST) to the first voltage supply, and
a fourth additional transistor (MS4) configured to connect the drain of the reset transistor (MRST) to a gate of the reset transistor (MRST).