US 11,962,439 B2
Fast equalization for jitter mitigation
Yehuda Azenkot, San Jose, CA (US); Georgios Takos, Mountian View, CA (US); and Bart R Zeydel, Fair Oaks, CA (US)
Assigned to MACOM Technology Solutions Holdings, Inc., Lowell, MA (US)
Appl. No. 17/440,159
Filed by MACOM Technology Solutions Holdings, Inc., Lowell, MA (US)
PCT Filed Mar. 20, 2020, PCT No. PCT/US2020/023802
§ 371(c)(1), (2) Date Sep. 16, 2021,
PCT Pub. No. WO2020/191273, PCT Pub. Date Sep. 24, 2020.
Claims priority of provisional application 62/821,348, filed on Mar. 20, 2019.
Prior Publication US 2022/0158876 A1, May 19, 2022
Int. Cl. H04L 25/03 (2006.01)
CPC H04L 25/03063 (2013.01) 19 Claims
OG exemplary drawing
 
1. A system for receiving signals transmitted via serial links, comprising:
an equalizer for accessing a digitized communications signal and producing an equalized output signal;
a fast equalization module for determining output data corresponding to said digitized communications signal, said fast equalization module comprising:
a filter to access an output of said equalizer;
a slicer module to access an output of said filter and produce a data output corresponding to said digitized communications signal;
a lookup table to provide filtering coefficients to said filter; and
a coefficient improvement module to improve said coefficients based on an error signal from said filter, wherein
said coefficient improvement module is configured to update said coefficients in said lookup table.