| CPC H03L 7/0818 (2013.01) [H03L 7/091 (2013.01); H03L 7/1075 (2013.01); H04L 7/02 (2013.01); H04L 7/033 (2013.01); H04L 7/0334 (2013.01)] | 14 Claims |
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1. A receiver, comprising:
an interface, configured to receive a sequence of data symbols, and further receive a clock signal for strobing the data symbols at selected positions of the data symbols;
a delay line configured to produce from the clock signal a middle sampling signal, an early sampling signal that precedes the middle sampling signal, and a late sampling signal that succeeds the middle sampling signal; and
circuitry, configured to:
sample the data symbols using the middle sampling signal, the early sampling signal and the late sampling signal, to produce an early error signal and a late error signal;
based on the early error signal and on the late error signal, configure the delay line to delay the middle sampling signal, the early sampling signal and the late sampling signal by separate respective delay values, so as to track both (i) a phase parameter indicative of a deviation between the middle sampling signal and the selected positions of the data symbols, and (ii) a width parameter indicative of a time duration of the data symbols; and
output the data symbols strobed using the middle sampling signal,
wherein the circuitry further comprises a width loop filter, and is further configured to track the width parameter by (i) applying a nonlinear function to the early error signal and the late error signal to produce a width error signal, and (ii) updating a value of the width parameter by applying the width loop filter to the width error signal.
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