US 11,962,277 B2
Switched-capacitor amplifier and pipelined analog-to-digital converter comprising the same
Fridolin Michel, Au (CH)
Assigned to AMS INTERNATIONAL AG, Jona (CH)
Appl. No. 17/779,823
Filed by ams International AG, Jona (CH)
PCT Filed Nov. 18, 2020, PCT No. PCT/EP2020/082503
§ 371(c)(1), (2) Date May 25, 2022,
PCT Pub. No. WO2021/104960, PCT Pub. Date Jun. 3, 2021.
Claims priority of application No. 19211524 (EP), filed on Nov. 26, 2019.
Prior Publication US 2023/0012330 A1, Jan. 12, 2023
Int. Cl. H03M 1/38 (2006.01); G04F 10/00 (2006.01); H03F 3/45 (2006.01); H03M 1/06 (2006.01)
CPC H03F 3/45179 (2013.01) [G04F 10/005 (2013.01); H03M 1/0607 (2013.01); H03F 2200/78 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A switched-capacitor amplifier, comprising:
a comparator having input terminals and an output terminal;
a sample capacitor coupled to one of the input terminals;
an amplification capacitor coupled to the one of the input terminals and through a first switch to a discharge current source and through a second switch to a charge current source;
a controller configured to operate the first and second switches in dependence on an output signal of the comparator; and
a closed loop control circuit configured to determine a delay of the comparator and control an offset of the comparator in response to the determined delay,
wherein the closed loop control circuit comprises a time-to-digital converter to determine a signal dependent on the delay of the comparator, wherein the signal is fed back to the comparator to set an offset of the comparator, and
wherein the closed loop control circuit further comprises an integrator connected between the time-to-digital converter and the comparator.