US 11,961,867 B2
Electronic device package and fabricating method thereof
Jin Young Kim, Seoul (KR); No Sun Park, Gwangju-si (KR); Yoon Joo Kim, Seoul (KR); Seung Jae Lee, Namyangju-si (KR); Se Woong Cha, Gwangju-si (KR); Sung Kyu Kim, Seoul (KR); and Ju Hoon Yoon, Namyangju-si (KR)
Assigned to Amkor Technology Singapore Holding Pte. Ltd., Singapore (SG)
Filed by Amkor Technology Singapore Holding Pte. Ltd., Singapore (SG)
Filed on Jun. 10, 2022, as Appl. No. 17/837,702.
Application 17/837,702 is a continuation of application No. 16/907,860, filed on Jun. 22, 2020, granted, now 11,362,128.
Application 16/907,860 is a continuation of application No. 16/423,589, filed on May 28, 2019, granted, now 10,692,918, issued on Jun. 23, 2020.
Application 16/423,589 is a continuation of application No. 15/823,987, filed on Nov. 28, 2017, granted, now 10,304,890, issued on May 28, 2019.
Application 15/823,987 is a continuation of application No. 15/248,687, filed on Aug. 26, 2016, granted, now 9,831,282, issued on Nov. 28, 2017.
Application 15/248,687 is a continuation of application No. 14/817,477, filed on Aug. 4, 2015, granted, now 9,431,447, issued on Aug. 30, 2016.
Application 14/817,477 is a continuation of application No. 14/082,482, filed on Nov. 18, 2013, granted, now 9,129,873, issued on Sep. 8, 2015.
Claims priority of application No. 10-2012-0131963 (KR), filed on Nov. 20, 2012.
Prior Publication US 2022/0375985 A1, Nov. 24, 2022
Int. Cl. H01L 27/146 (2006.01); G06V 40/12 (2022.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/528 (2006.01); H01L 21/56 (2006.01)
CPC H01L 27/14636 (2013.01) [H01L 23/49811 (2013.01); H01L 23/49827 (2013.01); H01L 23/5286 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 27/14618 (2013.01); H01L 27/14678 (2013.01); G06V 40/12 (2022.01); H01L 21/568 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/211 (2013.01); H01L 2224/214 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/181 (2013.01); H01L 2924/18162 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An electronic device comprising:
a semiconductor die comprising a first die side, a second die side opposite the first die side, and a plurality of lateral die sides extending between the first and second die sides, where the first die side comprises an integrated circuit and a bond pad;
an encapsulant that laterally covers the lateral die sides, where the encapsulant comprises a first encapsulant side, a second encapsulant side, and a plurality of lateral encapsulant sides extending between the first and second encapsulant sides;
a vertical interconnect structure passing through the encapsulant, the vertical interconnect structure comprising a first end and a second end;
a first conductor extending over the first die side and over the first encapsulant side, where the first conductor is coupled to the bond pad and to the first end of the vertical interconnect structure;
a second conductor coupled to the second end of the vertical interconnect structure;
a protection structure over the first die side and spaced apart from the first die side, wherein the protection structure forms a first exterior side of the electronic device with no conductive material exposed at the first exterior side;
a first dielectric material between the protection structure and the first die side, the first dielectric material configured to expose an area of the integrated circuit that is free of bond pads;
a second dielectric material on the second encapsulant side and laterally surrounding the second conductor, the second dielectric material forming a second exterior side of the electronic device, opposite the first exterior side; and
an external interconnect coupled to the second end of the vertical interconnect structure by the second conductor, wherein the external interconnect extends beyond the second exterior side formed by the second dielectric layer.