US 11,961,838 B2
Fin end plug structures for advanced integrated circuit structure fabrication
Byron Ho, Hillsboro, OR (US); Chun-Kuo Huang, Portland, OR (US); Erica Thompson, Beaverton, OR (US); Jeanne Luce, Hillsboro, OR (US); Michael L. Hattendorf, Portland, OR (US); Christopher P. Auth, Portland, OR (US); and Ebony L. Mays, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 3, 2022, as Appl. No. 17/736,029.
Application 16/906,680 is a division of application No. 15/859,351, filed on Dec. 30, 2017, granted, now 10,734,379, issued on Aug. 4, 2020.
Application 17/736,029 is a continuation of application No. 17/076,425, filed on Oct. 21, 2020, granted, now 11,380,683.
Application 17/076,425 is a continuation of application No. 16/906,680, filed on Jun. 19, 2020, granted, now 10,861,850, issued on Dec. 8, 2020.
Claims priority of provisional application 62/593,149, filed on Nov. 30, 2017.
Prior Publication US 2022/0262795 A1, Aug. 18, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/088 (2006.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/0886 (2013.01) [H01L 21/76232 (2013.01); H01L 21/823431 (2013.01); H01L 21/823481 (2013.01); H01L 21/823821 (2013.01); H01L 21/823878 (2013.01); H01L 27/0924 (2013.01); H01L 29/0653 (2013.01); H01L 29/66545 (2013.01); H01L 29/6656 (2013.01); H01L 29/66795 (2013.01); H01L 29/66818 (2013.01); H01L 29/7843 (2013.01); H01L 29/7846 (2013.01); H01L 29/7848 (2013.01); H01L 29/7851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a nanowire along a direction;
a first isolation structure over a first end of the nanowire, wherein the first isolation structure has a top surface above the top of the nanowire;
a gate structure comprising a gate electrode completely surrounding a channel region of the nanowire, wherein the gate structure is spaced apart from the first isolation structure along the direction; and
a second isolation structure over a second end of the nanowire, the second end opposite the first end, the second isolation structure spaced apart from the gate structure along the direction, wherein the second isolation structure has a top surface above the top of the nanowire, and wherein the first isolation structure and the second isolation structure each comprise a first dielectric material laterally surrounding a second dielectric material distinct from the first dielectric material, the second dielectric material having an upper surface, and wherein the wherein the first isolation structure and the second isolation structure both further comprise a third dielectric material laterally surrounded by an upper portion of the first dielectric material, the third dielectric material on the upper surface of the second dielectric material, and the third dielectric material distinct from the first dielectric material and from the second dielectric material.