US 11,961,742 B2
Semiconductor device and manufacturing method thereof
Jong Sik Paek, Incheon (KR); Doo Hyun Park, Anyang-si (KR); Seong Min Seo, Seoul (KR); Sung Geun Kang, Bucheon-si (KR); Yong Song, Seoul (KR); Wang Gu Lee, Goyang-si (KR); Eun Young Lee, Gumi-si (KR); Seo Yeon Ahn, Kwangju-si (KR); and Pil Je Sung, Seoul (KR)
Assigned to AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD., Singapore (SG)
Filed by Amkor Technology Singapore Holding Pte. Ltd., Singapore (SG)
Filed on Aug. 23, 2021, as Appl. No. 17/408,794.
Application 17/408,794 is a continuation of application No. 16/724,693, filed on Dec. 23, 2019, granted, now 11,101,144.
Application 16/724,693 is a continuation of application No. 16/134,590, filed on Sep. 18, 2018, granted, now 10,515,825, issued on Dec. 24, 2019.
Application 16/134,590 is a continuation of application No. 14/977,977, filed on Dec. 22, 2015, granted, now 10,079,157, issued on Sep. 18, 2018.
Claims priority of application No. 10-2014-0193744 (KR), filed on Dec. 30, 2014.
Prior Publication US 2022/0148886 A1, May 12, 2022
Int. Cl. H01L 21/48 (2006.01); H01L 23/14 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2023.01); H01L 21/60 (2006.01); H01L 23/00 (2006.01); H01L 23/15 (2006.01); H01L 23/31 (2006.01)
CPC H01L 21/4853 (2013.01) [H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 23/145 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49894 (2013.01); H01L 25/0655 (2013.01); H01L 2021/60022 (2013.01); H01L 23/147 (2013.01); H01L 23/15 (2013.01); H01L 23/3128 (2013.01); H01L 23/49827 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/81 (2013.01); H01L 24/83 (2013.01); H01L 24/92 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/13082 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81203 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/83192 (2013.01); H01L 2224/92125 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01); H01L 2924/18161 (2013.01); H01L 2924/19105 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An electronic device comprising:
an under layer (UL) comprising a top UL side, a bottom UL side, and a UL aperture that extends between the top UL side and the bottom UL side;
an interposer comprising:
a bottom interposer side coupled to the top UL side, a top interposer side, and a lateral interposer side;
an interposer dielectric layer at the bottom interposer side; and
an interposer conductive layer at the bottom interposer side, wherein at least a portion of the interposer conductive layer is exposed through the under layer (UL) by the UL aperture;
an upper dielectric layer on the top interposer side;
an upper conductive layer on the top interposer side;
a lower signal distribution structure on the bottom UL side and configured to electrically couple an interconnection structure to a bottom side of the interposer conductive layer through the UL aperture;
a first semiconductor die electrically coupled to the interposer through the upper conductive layer, wherein the first semiconductor die vertically covers only a first portion of the interposer; and
a second semiconductor die electrically coupled to the interposer through the upper conductive layer, wherein the second semiconductor die vertically covers only a second portion of the interposer.