US 11,961,577 B2
Testing of on-chip analog-mixed signal circuits using on-chip memory
Kumar Abhishek, Bee Cave, TX (US); Xiankun Jin, Austin, TX (US); and Mark Lehmann, Munich (DE)
Assigned to NXP USA, Inc., Austin, TX (US)
Filed by NXP USA, Inc., Austin, TX (US)
Filed on Jul. 5, 2022, as Appl. No. 17/810,671.
Prior Publication US 2024/0013848 A1, Jan. 11, 2024
Int. Cl. G11C 29/46 (2006.01); G11C 7/16 (2006.01); G11C 29/18 (2006.01); H03M 1/46 (2006.01)
CPC G11C 29/46 (2013.01) [G11C 7/16 (2013.01); G11C 29/18 (2013.01); H03M 1/462 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for on-chip testing of analog-to-digital converters (ADCs) in an integrated circuit, the ADCs including a first set of ADCs of a first ADC type and a second set of ADCs of a second ADC type, different from the first ADC type, the method comprising:
performing calibration of an N-bit differential digital-to-analog converter (DAC) used in performing the on-chip testing of the ADCs and storing a pair of calibration codes for each of 2N possible DAC input codes for the DAC in an on-chip memory;
testing the first set of ADCs using the pairs of calibration codes stored in the on-chip memory and a full N-bit resolution of the DAC; and
after the testing the first set of ADCs, testing the second set of ADCs using pairs of calibration codes corresponding to a reduced M-bit resolution of the DAC, wherein M and N are positive integers and M is less than N, wherein during the testing of the second set of ADCs, the method further comprises overwriting a portion of the calibration codes stored in the on-chip memory.