US 11,961,491 B2
Electro-optical device
Katsuya Anzai, Anpachi-cho (JP); Hideki Kawada, Anpachi-cho (JP); Hiroshi Matsuda, Gifu (JP); and Yukitada Iwasaki, Mizuho (JP)
Assigned to Japan Display Inc., Tokyo (JP)
Filed by Japan Display Inc., Tokyo (JP)
Filed on Jun. 1, 2023, as Appl. No. 18/204,482.
Application 18/204,482 is a continuation of application No. 17/876,951, filed on Jul. 29, 2022, granted, now 11,699,411.
Application 17/876,951 is a continuation of application No. 17/371,846, filed on Jul. 9, 2021, granted, now 11,404,017, issued on Aug. 2, 2022.
Application 17/371,846 is a continuation of application No. 16/906,807, filed on Jun. 19, 2020, granted, now 11,062,668, issued on Jul. 13, 2021.
Application 16/906,807 is a continuation of application No. 15/453,484, filed on Mar. 8, 2017, granted, now 10,692,453, issued on Jun. 23, 2020.
Application 15/453,484 is a continuation of application No. 12/211,425, filed on Sep. 16, 2008, granted, now 9,626,900, issued on Apr. 18, 2017.
Claims priority of application No. 2007-274733 (JP), filed on Oct. 23, 2007; application No. 2007-291596 (JP), filed on Nov. 9, 2007; application No. 2008-164114 (JP), filed on Jun. 24, 2008; and application No. 2008-164115 (JP), filed on Jun. 24, 2008.
Prior Publication US 2023/0306925 A1, Sep. 28, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G09G 3/36 (2006.01); G09G 3/20 (2006.01); G09G 3/3225 (2016.01); G09G 3/3266 (2016.01); G09G 3/3275 (2016.01); H10K 59/131 (2023.01)
CPC G09G 3/3677 (2013.01) [G09G 3/2096 (2013.01); G09G 3/3225 (2013.01); G09G 3/3266 (2013.01); G09G 3/3275 (2013.01); G09G 3/3648 (2013.01); G09G 3/3688 (2013.01); G09G 2300/0408 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0465 (2013.01); G09G 2310/0232 (2013.01); H10K 59/131 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An electro-optical device comprising:
a substrate;
gate lines extending in a first direction on the substrate;
a pixel area in which pixel electrodes are disposed;
an outer peripheral edge of the pixel area having a curved portion or a bent portion;
a first circuit block and a second circuit block which are arranged along the curved portion or the bent portion of the outer peripheral edge;
a first gate line included in the gate lines and connected to the first circuit block via a first relay line and a first output line, the first output line extending from the first circuit block, the first relay line connecting an end of the first gate line with an end of the first output line; and
a second gate line included in the gate lines and connected to the second circuit block via a second relay line and a second output line, the second output line extending from the second circuit block, the second relay line connecting an end of the second gate line with an end of the second output line,
wherein a second direction from the end of the first output line to the end of the first gate line is opposite to a third direction from the end of the second output line to the end of the second gate line,
wherein the second direction is orthogonal to the first direction,
wherein the third direction is orthogonal to the first direction.