US 11,961,179 B2
Fragment compression for coarse pixel shading
Prasoonkumar Surti, Folsom, CA (US); Abhishek R. Appu, El Dorado Hills, CA (US); Subhajit Dasgupta, Bangalore (IN); Srivallaba Mysore, Folsom, CA (US); Michael J. Norris, Folsom, CA (US); Vasanth Ranganathan, El Dorado Hills, CA (US); and Joydeep Ray, Folsom, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 24, 2023, as Appl. No. 18/305,511.
Application 18/305,511 is a continuation of application No. 17/723,328, filed on Apr. 18, 2022, granted, now 11,670,044.
Application 17/723,328 is a continuation of application No. 16/922,094, filed on Jul. 7, 2020, granted, now 11,315,311, issued on Apr. 26, 2022.
Application 16/922,094 is a continuation of application No. 15/493,214, filed on Apr. 21, 2017, granted, now 10,706,616, issued on Jul. 7, 2020.
Prior Publication US 2023/0386130 A1, Nov. 30, 2023
Int. Cl. G06T 15/80 (2011.01); G06T 1/20 (2006.01); G06T 1/60 (2006.01); G06T 15/00 (2011.01)
CPC G06T 15/80 (2013.01) [G06T 1/20 (2013.01); G06T 1/60 (2013.01); G06T 15/005 (2013.01); G06T 2210/52 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A graphics processing unit comprising:
a processing cluster to perform multi-rate shading via coarse pixel shading, wherein the processing cluster includes circuitry to vary a shading rate via a coarse pixel shading operation on a coarse pixel quad fragment to generate a coarse pixel quad and output the coarse pixel quad; and
a post-shader pixel pipeline including circuitry to:
receive the coarse pixel quad from the processing cluster;
perform coarse pixel operations on multiple coarse pixels within the coarse pixel quad via a pixel processing unit of the post-shader pixel pipeline; and
write, via the post-shader pixel pipeline, a processed coarse pixel quad to a render cache.