US 11,960,924 B2
Inter-thread interrupt signal sending based on interrupt configuration information of a PCI device and thread status information
Jianfeng Tan, Zhejiang (CN); Tiwei Bie, Zhejiang (CN); and Jielong Zhou, Zhejiang (CN)
Assigned to Alipay (Hangzhou) Information Technology Co., Ltd., Hangzhou (CN)
Filed by Alipay (Hangzhou) Information Technology Co., Ltd., Zhejiang (CN)
Filed on Jul. 14, 2023, as Appl. No. 18/353,020.
Application 18/353,020 is a continuation of application No. PCT/CN2022/116160, filed on Aug. 31, 2022.
Claims priority of application No. 202111282442.6 (CN), filed on Nov. 1, 2021.
Prior Publication US 2023/0359484 A1, Nov. 9, 2023
Int. Cl. G06F 9/48 (2006.01)
CPC G06F 9/4825 (2013.01) [G06F 9/4812 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for sending an interrupt signal between a first thread and a second thread, the method being executed by a peripheral component interconnect (PCI) device and comprising:
receiving, via a PCI bus, a notification message from a first processor in which a first thread is located, the notification message related to a virtual space address of the first thread to which a memory address of a memory mapped I/O (MMIO) memory of the PCI device is mapped;
generating an interrupt signal for a second thread in response to receiving the notification message;
configuring interrupt configuration information of the PCI device based on status information of the second thread that includes whether the second thread is running or a running status of the second thread, the configuring the interrupt configuration information including configuring an interrupt signal sending mechanism as sending the interrupt signal to a physical processor in a host kernel corresponding to a second processor in which the second thread is located in response to the second thread being assigned in a guest kernel and the second thread being not running and the second processor being a virtual processor, the physical processor being configured to wake up the virtual processor; and
sending the interrupt signal to the second processor in which the second thread is located based on the interrupt configuration information of the PCI device.