US 11,960,921 B2
Network functions virtualization platforms with function chaining capabilities
Abdel Hafiz Rabi, High Wycombe (GB); Allen Chen, Cupertino, CA (US); Mark Jonathan Lewis, Marlow Bottom (GB); and Jiefan Zhang, San Jose, CA (US)
Assigned to Altera Corporation, San Jose, CA (US)
Filed by Altera Corporation, San Jose, CA (US)
Filed on May 11, 2023, as Appl. No. 18/196,270.
Application 18/196,270 is a continuation of application No. 17/214,522, filed on Mar. 26, 2021, granted, now 11,687,358.
Application 17/214,522 is a continuation of application No. 16/683,093, filed on Nov. 13, 2019, granted, now 10,963,291, issued on Mar. 30, 2021.
Application 16/683,093 is a continuation of application No. 14/698,636, filed on Apr. 28, 2015, granted, now 10,489,178, issued on Nov. 26, 2019.
Prior Publication US 2023/0325230 A1, Oct. 12, 2023
Int. Cl. G06F 13/40 (2006.01); G06F 9/455 (2018.01); G06F 13/28 (2006.01)
CPC G06F 9/45558 (2013.01) [G06F 13/28 (2013.01); G06F 13/4022 (2013.01); G06F 2009/45595 (2013.01); G06F 2213/0038 (2013.01); G06F 2213/28 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A platform system, comprising:
one or more central processing units (CPUs);
storage to store custom logic data; and
a programmable logic device, wherein the programmable logic device comprises programmable logic configurable based on the custom logic data to provide:
a first hardware accelerator to perform a first function on data received from the one or more CPUs in response to a set of conditions being satisfied and to provide corresponding first output data; and
a second hardware accelerator to receive the first output data from the first hardware accelerator, to perform a second function on the first output data without routing the first output data external to the programmable logic device, and to provide corresponding second output data, wherein the one or more CPUs are configurable to call the first function and the second function.