CPC G06F 9/4403 (2013.01) [G06F 9/445 (2013.01)] | 24 Claims |
1. A compute device comprising:
a plurality of processors;
an error-correcting code (ECC) memory; and
circuitry included in at least a portion of the plurality of processors to execute a basic input/output system (BIOS), the BIOS to:
cause a hardware accelerator to initialize a plurality of memory addresses of the ECC memory via a plurality of direct-store operations that include the hardware accelerator to access the plurality of memory addresses without going through a cache hierarchy of any of the plurality of processors.
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