US 11,960,900 B2
Technologies for fast booting with error-correcting code memory
Murugasamy K. Nachimuthu, Beaverton, OR (US); Rajat Agarwal, Beaverton, OR (US); and Mohan J. Kumar, Aloha, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 28, 2019, as Appl. No. 16/729,321.
Prior Publication US 2020/0133683 A1, Apr. 30, 2020
Int. Cl. G06F 9/44 (2018.01); G06F 9/4401 (2018.01); G06F 9/445 (2018.01)
CPC G06F 9/4403 (2013.01) [G06F 9/445 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A compute device comprising:
a plurality of processors;
an error-correcting code (ECC) memory; and
circuitry included in at least a portion of the plurality of processors to execute a basic input/output system (BIOS), the BIOS to:
cause a hardware accelerator to initialize a plurality of memory addresses of the ECC memory via a plurality of direct-store operations that include the hardware accelerator to access the plurality of memory addresses without going through a cache hierarchy of any of the plurality of processors.