CPC G06F 9/3869 (2013.01) [G06F 9/30123 (2013.01)] | 21 Claims |
1. A processor comprising:
a plurality of parallel instruction pipes;
a register file comprising at least one shared register file read port configured to be shared across the plurality of parallel instruction pipes; and
control logic, operatively coupled to the register file, and configured to control the plurality of parallel instruction pipes to read from the at least one shared register file read port,
and wherein at least one of the plurality of parallel instruction pipes are configured to read from a plurality of non-shared register file read ports of the register file and read from the at least one shared register file read port.
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