CPC G06F 7/575 (2013.01) [G06F 1/03 (2013.01); G06F 7/5045 (2013.01); H03K 19/20 (2013.01); H03K 19/21 (2013.01)] | 20 Claims |
1. A circuit comprising:
a first arithmetic logic unit (ALU) slice comprising:
a plurality of lookup tables (LUTs) including a first LUT and a second LUT;
input connections configured to receive as input a portion of a first operand, a portion of a second operand, a first carry-in bit from a second ALU slice, and a second carry-in bit from a third ALU slice;
a multiplexer controlled by the second carry-in bit; and
output connections configured to provide, as output, a set of sum bits and a carry-out bit, the sum bits containing the sum of the input portion of the first operand, the input portion of the second operand, and the first carry-in bit;
wherein each of the plurality of LUTs receives the portion of the first operand and portion of the second operand as inputs.
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