US 11,960,857 B2
Adder circuit using lookup tables
Christopher C. LaFrieda, Ridgefield, NJ (US); and Virantha N. Ekanayake, Baltimore, MD (US)
Assigned to Achronix Semiconductor Corporation, Santa Clara, CA (US)
Filed by Achronix Semiconductor Corporation, Santa Clara, CA (US)
Filed on May 8, 2023, as Appl. No. 18/144,609.
Application 18/144,609 is a continuation of application No. 17/134,838, filed on Dec. 28, 2020, granted, now 11,714,607.
Prior Publication US 2023/0315390 A1, Oct. 5, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 7/575 (2006.01); G06F 1/03 (2006.01); G06F 7/504 (2006.01); H03K 19/20 (2006.01); H03K 19/21 (2006.01)
CPC G06F 7/575 (2013.01) [G06F 1/03 (2013.01); G06F 7/5045 (2013.01); H03K 19/20 (2013.01); H03K 19/21 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit comprising:
a first arithmetic logic unit (ALU) slice comprising:
a plurality of lookup tables (LUTs) including a first LUT and a second LUT;
input connections configured to receive as input a portion of a first operand, a portion of a second operand, a first carry-in bit from a second ALU slice, and a second carry-in bit from a third ALU slice;
a multiplexer controlled by the second carry-in bit; and
output connections configured to provide, as output, a set of sum bits and a carry-out bit, the sum bits containing the sum of the input portion of the first operand, the input portion of the second operand, and the first carry-in bit;
wherein each of the plurality of LUTs receives the portion of the first operand and portion of the second operand as inputs.