US 11,960,854 B2
Time domain multiply and accumulate system
Ravinder Reddy Rachala, Austin, TX (US); Stephen Victor Kosonocky, Fort Collins, CO (US); and Miguel Rodriguez, Golden, CO (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Sep. 22, 2020, as Appl. No. 17/028,723.
Prior Publication US 2022/0091822 A1, Mar. 24, 2022
Int. Cl. G06F 7/544 (2006.01); H03K 19/20 (2006.01); H03K 21/08 (2006.01)
CPC G06F 7/5443 (2013.01) [H03K 21/08 (2013.01); H03K 19/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A multiply-accumulate circuit comprising:
a series of ripple counter units comprising:
a first ripple counter unit comprising a ripple counter having a first input coupled to receive a respective target signal, a second input coupled to receive a respective counter reset value, a third input coupled to receive a respective stop count value, and a counter output;
a series of additional ripple counter units comprising a ripple counter having a first input coupled to receive a respective target signal, a second input coupled to receive a respective counter reset value, a third input coupled to receive a respective stop count value, and a counter output; and an adder circuit coupled to receive the counter output and a sum from a prior adder circuit output in the series of ripple counter units and produce a sum therefrom at an output; and
wherein the ripple counter of each ripple counter unit is controlled by the respective stop count value to adjust a respective ripple counter sampling period with respect to a reference clock signal to scale the respective counter output.