US 11,960,813 B2
Automatic redistribution layer via generation
Rajagopalan Venkatramani, Hsinchu (TW); Renato Dimatula Gaddi, Markham (CA); Liane Martinez, Markham (CA); Warren Alexander Santos, Markham (CA); and Dennis Glenn Lozanta Surell, Markham (CA)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US); and ATI Technologies ULC, Markham (CA)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US); and ATI Technologies ULC, Markham (CA)
Filed on Dec. 27, 2021, as Appl. No. 17/562,833.
Claims priority of provisional application 63/228,552, filed on Aug. 2, 2021.
Prior Publication US 2023/0036608 A1, Feb. 2, 2023
Int. Cl. G06F 30/3953 (2020.01); G06F 30/398 (2020.01)
CPC G06F 30/3953 (2020.01) [G06F 30/398 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A processor comprising:
circuitry configured to:
receive a plurality of attributes corresponding to placement of a plurality of vias between adjacent metal layers of a plurality of metal layers; and
generate data indicative of a placement of the plurality of vias in via layers between the adjacent metal layers, based at least in part on the attributes and an identification of an overlap region in the adjacent metal layers, wherein the attributes identify a first via layer is to have vias generated both prior to and after generation of vias of a second via layer.