CPC G06F 30/3953 (2020.01) [G06F 30/398 (2020.01)] | 20 Claims |
1. A processor comprising:
circuitry configured to:
receive a plurality of attributes corresponding to placement of a plurality of vias between adjacent metal layers of a plurality of metal layers; and
generate data indicative of a placement of the plurality of vias in via layers between the adjacent metal layers, based at least in part on the attributes and an identification of an overlap region in the adjacent metal layers, wherein the attributes identify a first via layer is to have vias generated both prior to and after generation of vias of a second via layer.
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