CPC G06F 3/0679 (2013.01) [G06F 11/1048 (2013.01)] | 20 Claims |
1. An apparatus, comprising:
a first number of memory units configured for host data, each memory unit of the first number of memory units further comprising:
a primary memory die configured for a respective first portion of the host data and coupled to a respective first substrate via a respective first external data link; and
a secondary memory die configured for a respective second portion of the host data and coupled to the primary memory die via a respective first internal data link; and
a second memory unit configured for parity data to perform an error correction operation on the host data, the second memory unit further comprising:
a primary memory die configured for a respective first portion of the parity data and coupled to a respective second substrate via a respective second external data link; and
a secondary memory die configured for a respective second portion of the parity data and coupled to the primary memory die via a respective second internal data link.
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