US 11,960,776 B2
Data protection for stacks of memory dice
Marco Sforzin, Cernusco sul Naviglio (IT); and Paolo Amato, Treviglio (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 2, 2022, as Appl. No. 17/831,263.
Prior Publication US 2023/0393789 A1, Dec. 7, 2023
Int. Cl. G06F 11/10 (2006.01); G06F 3/06 (2006.01); G06F 11/07 (2006.01); G06F 11/30 (2006.01); G06F 13/16 (2006.01); G06F 13/28 (2006.01); H03M 13/11 (2006.01); H03M 13/15 (2006.01)
CPC G06F 3/0679 (2013.01) [G06F 11/1048 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a first number of memory units configured for host data, each memory unit of the first number of memory units further comprising:
a primary memory die configured for a respective first portion of the host data and coupled to a respective first substrate via a respective first external data link; and
a secondary memory die configured for a respective second portion of the host data and coupled to the primary memory die via a respective first internal data link; and
a second memory unit configured for parity data to perform an error correction operation on the host data, the second memory unit further comprising:
a primary memory die configured for a respective first portion of the parity data and coupled to a respective second substrate via a respective second external data link; and
a secondary memory die configured for a respective second portion of the parity data and coupled to the primary memory die via a respective second internal data link.