CPC G06F 3/0632 (2013.01) [G06F 3/0614 (2013.01); G06F 3/0658 (2013.01); G06F 3/0673 (2013.01); G11C 7/22 (2013.01); G11C 2207/2254 (2013.01)] | 20 Claims |
1. An apparatus comprising:
a memory; and
a memory controller coupled to the memory, wherein the memory controller includes a calibration circuit configured to:
perform a reference voltage calibration to determine a reference voltage used to distinguish between logic values read from the memory, wherein the reference voltage calibration comprises performing a plurality of horizontal calibrations at different reference voltage values, and wherein ones of the horizontal calibrations comprise determining a range of delay values applied to a data strobe signal at which valid data is read from the memory;
determine scores corresponding to ones of the plurality of horizontal calibrations, wherein a score for a particular one of the plurality of horizontal calibrations is based on a corresponding range of delay values and a reference voltage margin; and
select a calibrated reference voltage based on the scores corresponding to ones of the plurality of horizontal calibrations.
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