CPC G06F 3/0622 (2013.01) [G06F 3/0655 (2013.01); G06F 3/0673 (2013.01); G06N 3/08 (2013.01)] | 20 Claims |
1. An integrated circuit, comprising:
a first microsector, comprising:
memory configured to store first data and second data;
a data register configured to write the first data to the memory;
a first shift register configured to receive the second data from the memory, wherein the second data bypasses the data register in transmission to the first shift register; and
a row controller coupled to the first microsector, wherein the row controller receives the second data in response to transmitting a control signal to the first shift register to instruct a read of the second data.
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