US 11,960,734 B2
Logic fabric based on microsector infrastructure with data register having scan registers
Sean R Atsatt, Santa Cruz, CA (US); and Ilya K. Ganusov, San Jose, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 25, 2020, as Appl. No. 17/033,348.
Prior Publication US 2021/0011636 A1, Jan. 14, 2021
Int. Cl. G06F 3/06 (2006.01); G06N 3/08 (2023.01); H03K 19/17724 (2020.01)
CPC G06F 3/0622 (2013.01) [G06F 3/0655 (2013.01); G06F 3/0673 (2013.01); G06N 3/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a first microsector, comprising:
memory configured to store first data and second data;
a data register configured to write the first data to the memory;
a first shift register configured to receive the second data from the memory, wherein the second data bypasses the data register in transmission to the first shift register; and
a row controller coupled to the first microsector, wherein the row controller receives the second data in response to transmitting a control signal to the first shift register to instruct a read of the second data.