US 11,960,567 B2
Implementing fundamental computational primitives using a matrix multiplication accelerator (MMA)
Arthur John Redfern, Plano, TX (US); Timothy David Anderson, University Park, TX (US); Kai Chirca, Dallas, TX (US); Chenchi Luo, Plano, TX (US); and Zhenhua Yu, Santa Clara, CA (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jul. 4, 2021, as Appl. No. 17/367,389.
Application 17/367,389 is a continuation of application No. 15/907,356, filed on Feb. 28, 2018, granted, now 11,086,967.
Claims priority of provisional application 62/465,620, filed on Mar. 1, 2017.
Prior Publication US 2021/0334337 A1, Oct. 28, 2021
Int. Cl. G06F 17/16 (2006.01); G06F 17/14 (2006.01); G06N 3/045 (2023.01); G06N 3/063 (2023.01)
CPC G06F 17/16 (2013.01) [G06F 17/141 (2013.01); G06N 3/045 (2023.01); G06N 3/063 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A matrix multiplication accelerator comprising:
a first formatting component having a first input and a first output;
a second formatting component having a second input and second output;
a third formatting component having a third input and a third output;
a row offset component having an offset input coupled to the second output, and an offset output;
a first memory having a first matrix input coupled to the first output, and a first matrix output;
a second memory having a second matrix input coupled to the offset output, and a second matrix output;
a nonlinearity component having a nonlinearity input, and a nonlinearity output coupled to the third input;
a third memory having a third matrix input, and a third matrix output coupled to the nonlinearity input; and
a matrix multiplication component coupled to the first matrix output, the second matrix output, and the third matrix input.