CPC G06F 13/1673 (2013.01) [G06F 13/4068 (2013.01); G11C 5/02 (2013.01); G11C 7/10 (2013.01); G11C 7/1012 (2013.01); G11C 7/1021 (2013.01); G11C 7/106 (2013.01); G11C 7/1066 (2013.01); G11C 7/1072 (2013.01); G11C 7/1087 (2013.01); G11C 7/1093 (2013.01); G11C 7/222 (2013.01); G11C 8/18 (2013.01); G11C 11/4076 (2013.01); G11C 11/4093 (2013.01); G11C 11/4096 (2013.01); G11C 11/419 (2013.01); G11C 29/022 (2013.01); G11C 29/023 (2013.01); G11C 29/028 (2013.01)] | 20 Claims |
1. A dynamic random access memory (DRAM) die, comprising:
an array of DRAM storage cells;
a primary data interface, in a first mode of operation, to receive a serialized write data stream from a first integrated circuit (IC) chip, the primary interface to deserialize the write data stream into a first plurality of data streams; and
a secondary data interface, in the first mode of operation, to transmit the first plurality of data streams to a second DRAM die during an interval associated with write operations.
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