US 11,960,418 B2
Semiconductor memory systems with on-die data buffering
Frederick A. Ware, Los Altos Hills, CA (US); Amir Amirkhany, Sunnyvale, CA (US); Suresh Rajan, Fremont, CA (US); Mohammad Hekmat, Mountain View, CA (US); and Dinesh Patil, Sunnyvale, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Oct. 13, 2022, as Appl. No. 17/965,684.
Application 17/965,684 is a continuation of application No. 17/081,909, filed on Oct. 27, 2020, granted, now 11,487,679.
Application 17/081,909 is a continuation of application No. 16/546,694, filed on Aug. 21, 2019, granted, now 10,831,685, issued on Nov. 10, 2020.
Application 16/546,694 is a continuation of application No. 15/333,001, filed on Oct. 24, 2016, granted, now 10,402,352, issued on Sep. 3, 2019.
Application 15/333,001 is a continuation of application No. 14/683,080, filed on Apr. 9, 2015, granted, now 9,501,433, issued on Nov. 22, 2016.
Application 14/683,080 is a continuation of application No. 14/023,970, filed on Sep. 11, 2013, granted, now 9,009,400, issued on Apr. 14, 2015.
Claims priority of provisional application 61/714,666, filed on Oct. 16, 2012.
Prior Publication US 2023/0120661 A1, Apr. 20, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/10 (2006.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); G11C 5/02 (2006.01); G11C 7/22 (2006.01); G11C 8/18 (2006.01); G11C 11/4076 (2006.01); G11C 11/4093 (2006.01); G11C 11/4096 (2006.01); G11C 11/419 (2006.01); G11C 29/02 (2006.01)
CPC G06F 13/1673 (2013.01) [G06F 13/4068 (2013.01); G11C 5/02 (2013.01); G11C 7/10 (2013.01); G11C 7/1012 (2013.01); G11C 7/1021 (2013.01); G11C 7/106 (2013.01); G11C 7/1066 (2013.01); G11C 7/1072 (2013.01); G11C 7/1087 (2013.01); G11C 7/1093 (2013.01); G11C 7/222 (2013.01); G11C 8/18 (2013.01); G11C 11/4076 (2013.01); G11C 11/4093 (2013.01); G11C 11/4096 (2013.01); G11C 11/419 (2013.01); G11C 29/022 (2013.01); G11C 29/023 (2013.01); G11C 29/028 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A dynamic random access memory (DRAM) die, comprising:
an array of DRAM storage cells;
a primary data interface, in a first mode of operation, to receive a serialized write data stream from a first integrated circuit (IC) chip, the primary interface to deserialize the write data stream into a first plurality of data streams; and
a secondary data interface, in the first mode of operation, to transmit the first plurality of data streams to a second DRAM die during an interval associated with write operations.