US 11,960,405 B2
Multi-tile memory management mechanism
Zack S. Waters, Portland, OR (US); Travis Schluessler, Berthoud, CO (US); Michael Apodaca, Folsom, CA (US); and Ankur Shah, Folsom, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 30, 2022, as Appl. No. 18/148,749.
Application 18/148,749 is a division of application No. 16/802,427, filed on Feb. 26, 2020, granted, now 11,580,027.
Prior Publication US 2023/0244609 A1, Aug. 3, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/0882 (2016.01); G06F 9/4401 (2018.01); G06F 9/50 (2006.01); G06F 9/54 (2006.01); G06F 11/30 (2006.01); G06F 12/06 (2006.01); G06F 12/0837 (2016.01); G06F 12/1045 (2016.01)
CPC G06F 12/0882 (2013.01) [G06F 9/4411 (2013.01); G06F 9/5016 (2013.01); G06F 9/544 (2013.01); G06F 11/3006 (2013.01); G06F 11/3037 (2013.01); G06F 12/0607 (2013.01); G06F 12/0837 (2013.01); G06F 12/1054 (2013.01); G06F 12/1063 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A graphics processor for a multi-tile architecture, comprising:
a first graphics device having a local memory;
a second graphics device having a local memory; and
a processing resource that is configured to execute instructions to provide a single virtual allocation with a common virtual address range to interleave physical pages of a shared resource to local memory of the first and second graphics devices.