US 11,960,404 B2
Method and apparatus for reducing the latency of long latency memory requests
Jagadish B. Kotra, Austin, TX (US); and John Kalamatianos, Boxborough, MA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Sep. 23, 2020, as Appl. No. 17/029,976.
Prior Publication US 2022/0091986 A1, Mar. 24, 2022
Int. Cl. G06F 12/0875 (2016.01)
CPC G06F 12/0875 (2013.01) [G06F 2212/452 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a queue comprising a first memory request with a first priority and a second memory request with a second priority higher than the first priority; and
circuitry configured to:
store an indication that the first memory request is a long-latency request, based at least in part on execution of the first memory request causing a page table walk; and
cause the first memory request to issue prior to the second memory request, responsive to the indication that the first memory request is a long-latency request.