CPC G06F 12/0875 (2013.01) [G06F 2212/452 (2013.01)] | 20 Claims |
1. An apparatus comprising:
a queue comprising a first memory request with a first priority and a second memory request with a second priority higher than the first priority; and
circuitry configured to:
store an indication that the first memory request is a long-latency request, based at least in part on execution of the first memory request causing a page table walk; and
cause the first memory request to issue prior to the second memory request, responsive to the indication that the first memory request is a long-latency request.
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