US 11,960,399 B2
Relaxed invalidation for cache coherence
Akhil Arunkumar, Santa Clara, CA (US); Tarun Nakra, Austin, TX (US); Maxim V. Kazakov, San Diego, CA (US); and Milind N. Nemlekar, San Diego, CA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed on Dec. 21, 2021, as Appl. No. 17/558,034.
Prior Publication US 2023/0195628 A1, Jun. 22, 2023
Int. Cl. G06F 12/0811 (2016.01); G06F 12/0853 (2016.01); G06F 13/16 (2006.01)
CPC G06F 12/0811 (2013.01) [G06F 12/0853 (2013.01); G06F 13/1642 (2013.01); G06F 13/1668 (2013.01)] 28 Claims
OG exemplary drawing
 
1. A method comprising:
generating one or more notifications of a write operation associated with a first private cache of a plurality of private caches responsive to the write operation, the first private cache being associated with one processing core of a plurality of processing cores;
delaying transmission of the one or more notifications of the write operation to any private caches of the plurality of private caches until a synchronization event occurs; and
responsive to the synchronization event, providing the one or more notifications to at least one of the private caches.