US 11,960,339 B2
Multi-die stacked power delivery
Eric J. Chapman, Austin, TX (US); Alan D. Smith, Austin, TX (US); and Edward Chang, FT. Collins, CO (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed on Jul. 9, 2021, as Appl. No. 17/371,459.
Prior Publication US 2023/0009881 A1, Jan. 12, 2023
Int. Cl. G06F 1/28 (2006.01); H01L 25/18 (2023.01)
CPC G06F 1/28 (2013.01) [H01L 25/18 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A processor, comprising:
a first base integrated circuit (IC) die configured to provide, based at least in part on an indication of a configuration of a first plurality of compute dies stacked on top of the first base IC die, a different power domain to each of the first plurality of compute dies, each of the different power domains corresponding to a different power plane,
wherein the first base IC die is configured to unify power domains of two or more voltage regulator networks of a plurality of voltage regulator networks to provide a first independent power plane to a first compute die of the first plurality of compute dies.