US 11,960,155 B1
Two-dimensional metasurfaces with integrated capacitors and active-matrix driver routing
Gleb M. Akselrod, Kenmore, WA (US); and Erik Edward Josberger, Renton, WA (US)
Assigned to Lumotive, Inc., Redmond, WA (US)
Filed by Lumotive, Inc., Redmond, WA (US)
Filed on Oct. 5, 2023, as Appl. No. 18/481,936.
Int. Cl. G02F 1/015 (2006.01); G02F 1/01 (2006.01); G02F 1/03 (2006.01); G02F 1/035 (2006.01)
CPC G02F 1/0151 (2021.01) [G02F 1/0113 (2021.01); G02F 1/0338 (2013.01); G02F 1/035 (2013.01); G02F 2203/15 (2013.01)] 35 Claims
OG exemplary drawing
 
1. An optical metasurface device, comprising:
an optical resonator layer with a two-dimensional array of metallic pillars arranged in rows and columns, and a tunable dielectric material that has a tunable refractive index positioned within gaps between adjacent metallic pillars in each row of metallic pillars;
an optically reflective layer positioned between a substrate layer and the optical resonator layer to reflect incident optical radiation;
driver routing layers with a row conductor for each row of metallic pillars and a column conductor for each column of metallic pillars;
a transistor layer with a plurality of transistor devices, wherein each transistor device is connected to and configured to be selectively driven by one of the row conductors and one of the column conductors, wherein a subset of the metallic pillars in the optical resonator layer are active metallic pillars, and wherein each active metallic pillar is connected to at least one of the transistor devices in the transistor layer; and
a controller to selectively apply a pattern of voltages to the active metallic pillars by:
sequentially driving a voltage on each row conductor, according to a refresh rate, to temporarily activate the transistor devices of the row of metallic pillars associated with each respective row conductor for a refresh cycle time; and
driving each column conductor to apply a target voltage to each active metallic pillar in the row of metallic pillars associated with the temporarily activated transistor devices during each respective refresh cycle time.