US 11,959,962 B2
Integrated circuit package with internal circuitry to detect external component parameters and parasitics
Chengyue Yu, San Diego, CA (US); Hua Guan, San Diego, CA (US); Yingjie Chen, Atlanta, GA (US); Fan Yang, Singapore (SG); Yufei Pan, Singapore (SG); Jize Jiang, Singapore (SG); and Shamim Ahmed, Mesa, AZ (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Jun. 23, 2022, as Appl. No. 17/808,357.
Prior Publication US 2023/0417828 A1, Dec. 28, 2023
Int. Cl. G01R 31/28 (2006.01)
CPC G01R 31/2896 (2013.01) [G01R 31/2853 (2013.01); G01R 31/2891 (2013.01)] 32 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) package comprising:
a pin for coupling to a component external to the IC package; and
at least one of a resistance detector, an inductance detector, or a capacitance detector coupled to the pin and configured to detect at least one of a resistance, an inductance, or a capacitance, respectively, of a lumped parameter model for the component external to the IC package and for parasitics associated with at least one of the component, the pin, or a connection between the component and the pin, wherein the capacitance detector includes a current source, a switch coupled between the current source and the pin, an analog-to-digital converter (ADC), and a sample-and-hold circuit coupled between the pin and the ADC.