US 12,279,538 B2
Phase change memory unit and preparation method therefor
Min Zhong, Shanghai (CN); Ming Li, Shanghai (CN); Shoumian Chen, Shanghai (CN); and Gaoming Feng, Shanghai (CN)
Assigned to Shanghai Integrated Circuit Equipment & Materials Industry Innovation Center Co., Ltd, Shanghai (CN); and SHANGHAI IC R&D CENTER CO., LTD., Shanghai (CN)
Appl. No. 17/786,526
Filed by Shanghai Integrated Circuit Equipment & Materials Industry Innovation Center Co., Ltd., Shanghai (CN); and SHANGHAI IC R&D CENTER CO., LTD., Shanghai (CN)
PCT Filed Jul. 23, 2020, PCT No. PCT/CN2020/103754
§ 371(c)(1), (2) Date Jun. 16, 2022,
PCT Pub. No. WO2021/120620, PCT Pub. Date Jun. 24, 2021.
Claims priority of application No. 201911315353.X (CN), filed on Dec. 19, 2019; and application No. 201911315361.4 (CN), filed on Dec. 19, 2019.
Prior Publication US 2023/0363299 A1, Nov. 9, 2023
Int. Cl. H10N 70/00 (2023.01); H10B 63/00 (2023.01); H10B 63/10 (2023.01); H10N 70/20 (2023.01)
CPC H10N 70/8413 (2023.02) [H10B 63/10 (2023.02); H10B 63/20 (2023.02); H10N 70/023 (2023.02); H10N 70/066 (2023.02); H10N 70/231 (2023.02); H10N 70/8265 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A phase change memory unit, wherein comprising from bottom to top: a bottom electrode, a heating electrode, a phase change unit and a top electrode, the phase change unit is a longitudinally arranged column, which comprise a cylindrical selector layer, a circular barrier layer and a circular phase change material layer form inside to outside; wherein, the bottom electrode, the heating electrode and the circular phase change material layer are sequentially connected, and the selector layer is connected to the top electrode.