| CPC H10N 70/841 (2023.02) [H01L 23/5283 (2013.01); H10B 63/24 (2023.02); H10B 63/84 (2023.02); H10N 70/011 (2023.02); H10N 70/231 (2023.02)] | 20 Claims |
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1. A semiconductor memory device comprising:
an inter-wiring insulation film on a substrate;
a word line extending in a first direction, in the inter-wiring insulation film;
a barrier insulation film that is on an upper surface of the inter-wiring insulation film;
a barrier conductive pattern electrically connected to the word line, in the barrier insulation film;
a memory cell electrically connected to the barrier conductive pattern and including a lower electrode pattern that is in direct contact with the barrier conductive pattern, a selection pattern on the lower electrode pattern, and a variable resistor pattern on the selection pattern; and
a second wiring pattern extending in a second direction intersecting the first direction, on the memory cell,
wherein a width of the barrier conductive pattern in the second direction is different from a width in the second direction of the lower electrode pattern and is different from a width in the second direction of the word line, and
wherein the lower electrode pattern comprises a metal, a metal nitride, or a combination thereof.
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