US 12,279,460 B2
Electrostatic discharge protection device
Ming-Hui Chen, Hsinchu (TW); Chih-Feng Lin, Taipei (TW); Chiu-Tsung Huang, Hsinchu (TW); and Hsiang-Hung Chang, Hsinchu County (TW)
Assigned to Powerchip Semiconductor Manufacturing Corporation, Hsinchu (TW)
Filed by Powerchip Semiconductor Manufacturing Corporation, Hsinchu (TW)
Filed on Aug. 9, 2022, as Appl. No. 17/884,533.
Claims priority of application No. 111121229 (TW), filed on Jun. 8, 2022.
Prior Publication US 2023/0411382 A1, Dec. 21, 2023
Int. Cl. H10D 89/60 (2025.01)
CPC H10D 89/811 (2025.01) 17 Claims
OG exemplary drawing
 
1. An electrostatic discharge (ESD) protection device, comprising:
a P-type substrate;
a first transistor comprising:
a first gate located on the P-type substrate;
a first N-type source region and an N-type drain region located in the P-type substrate on two sides of the first gate;
a first P-type body region located in the P-type substrate, wherein the first P-type body region and the first N-type source region are located on the same side of the first gate, and the first N-type source region is located in the first P-type body region; and
a first P-type bulk region located in the first P-type body region, wherein the first N-type source region is located between the first P-type bulk region and the first gate;
a second transistor comprising:
a second gate located on the P-type substrate;
a second N-type source region and the N-type drain region located in the P-type substrate on two sides of the second gate, wherein the N-type drain region is located between the first gate and the second gate;
a second P-type body region located in the P-type substrate, wherein the second P-type body region and the second N-type source region are located on the same side of the second gate, and the second N-type source region is located in the second P-type body region; and
a second P-type bulk region located in the second P-type body region, wherein the second N-type source region is located between the second P-type bulk region and the second gate;
an N-type drift region located in the P-type substrate between the first gate and the second gate and located directly below a portion of the first gate and directly below a portion of the second gate, wherein the N-type drain region is located in the N-type drift region; and
a P-type barrier region located in the P-type substrate below the N-type drift region, wherein the P-type barrier region has an overlapping portion overlapping the N-type drift region, and there is at least one first opening in the overlapping portion,
wherein there are a second opening and a third opening in the P-type barrier region,
the second opening is located directly below the first P-type body region, and
the third opening is located directly below the second P-type body region.