| CPC H10D 86/60 (2025.01) [G09G 3/3225 (2013.01); H10D 86/431 (2025.01); H10D 86/471 (2025.01); G09G 2300/0426 (2013.01); G09G 2300/0465 (2013.01); G09G 2300/0814 (2013.01); G09G 2300/0842 (2013.01); H10D 86/423 (2025.01); H10K 59/1213 (2023.02)] | 18 Claims |
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1. A display panel, comprising:
a base substrate;
a third transistor and a fourth transistor;
wherein:
the third transistor and the fourth transistor are formed on the base substrate;
the third transistor includes a sixth gate electrode, a third active layer, a third source electrode, and a third drain electrode;
the third active layer includes an oxide semiconductor;
the fourth transistor includes an eighth gate electrode, a fourth active layer, a fourth source electrode, and a fourth drain electrode; and
the fourth active layer includes another oxide semiconductor;
along a direction perpendicular to the base substrate, a distance between the sixth gate electrode and the third active layer is D6, a channel region of the third transistor defined by the sixth gate electrode is a sixth channel region, a length of the sixth channel region is L6, and a sixth area S6=L6×D6; and
along the direction perpendicular to the base substrate, a distance between the eighth gate electrode and the fourth active layer is D8, a channel region of the fourth transistor defined by the eighth gate electrode is an eighth channel region, a length of the eighth channel region is L8, and an eighth area S8=L8×D8; and
a pixel circuit and a drive circuit providing a drive signal for the pixel circuit, wherein the third transistor is a drive transistor of the pixel circuit, the fourth transistor is a switch transistor of the pixel circuit, and S6>S8, wherein:
the third transistor further includes a fifth gate electrode, and along the direction perpendicular to the base substrate, a distance between the fifth gate electrode and the third active layer is D5, a channel region of the third transistor defined by the fifth gate electrode is a fifth channel region, a length of the fifth channel region is L5, and a fifth area S5=L5×D5,
the fourth transistor further includes a seventh gate electrode, and along the direction perpendicular to the base substrate, a distance between the seventh gate electrode and the fourth active layer is D7, a channel region of the fourth transistor defined by the seventh gate electrode is a seventh channel region, a length of the seventh channel region is L7, and a seventh area S7=L7×D7, and
(S6−S5)> (S8−S7),
wherein S8≠S7.
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