| CPC H10D 64/513 (2025.01) [H01L 21/76224 (2013.01); H10D 30/668 (2025.01); H10D 64/516 (2025.01); H10D 64/518 (2025.01)] | 20 Claims |
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1. A semiconductor device, comprising:
an epitaxial layer;
at least one gate trench comprising a lower gate trench and an upper gate trench, a width of the lower gate trench being less than a width of the upper gate trench;
at least one trench gate structure disposed in the at least one gate trench, wherein the at least one trench gate structure comprises:
a bottom gate structure disposed in a lower portion of the lower gate trench, wherein the bottom gate structure comprises a first gate electrode and a first gate dielectric layer;
a middle gate structure disposed in an upper portion of the lower gate trench, wherein the middle gate structure comprises a second gate electrode and a second gate dielectric layer, a thickness of the second gate dielectric layer being less than a thickness of the first gate dielectric layer; and
a top gate structure disposed in the upper gate trench, wherein the top gate structure comprises a third gate electrode and a third gate dielectric layer, a thickness of the third gate dielectric layer being less than the thickness of the second gate dielectric layer,
wherein the first gate electrode, the second gate electrode, and the third gate electrode are separated from each other.
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