US 12,279,454 B2
Zero expansion in a replacement metal gate process with a spacer
Youseung Jin, Ballston Spa, NY (US); Elnatan Mataev, Poughkeepsie, NY (US); Jonathan Fry, Fishkill, NY (US); and Dominic Rossillo, Highland, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Sep. 23, 2021, as Appl. No. 17/482,731.
Prior Publication US 2023/0092313 A1, Mar. 23, 2023
Int. Cl. H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H10B 10/00 (2023.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 64/01 (2025.01); H10D 64/66 (2025.01)
CPC H10D 64/017 (2025.01) [H10B 10/12 (2023.02); H10B 10/18 (2023.02); H10D 30/024 (2025.01); H10D 30/62 (2025.01); H10D 64/671 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure comprising:
a functional gate structure located on a semiconductor channel material structure, wherein the functional gate structure has an outermost sidewall that is substantially perpendicular relative to a planar horizontal surface of the semiconductor channel material structure;
source/drain regions located on a surface of the semiconductor channel material structure and on either side of the functional gate structure;
a dielectric spacer located laterally adjacent to the functional gate structure, wherein the dielectric spacer has a vertical sidewall facing the outermost sidewall of the functional gate structure and wherein the dielectric spacer entirely separates the functional gate structure from the source/drain regions; and
a dipole material spacer located between the outermost sidewall of the functional gate structure and the dielectric spacer, wherein the dielectric spacer and the dipole spacer both land directly on the semiconductor channel material structure.