| CPC H10D 62/116 (2025.01) [H10D 30/65 (2025.01); H10D 64/516 (2025.01)] | 30 Claims |
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1. A semiconductor device comprising:
a source region, a drain region, and a gate dielectric layer formed on a substrate;
a body region formed to surround the source region;
a gate electrode formed on the gate dielectric layer;
a first dielectric pattern, formed contacting a sidewall of the gate electrode, extending from the source region onto a portion of an upper surface of the gate electrode;
a spacer formed on another sidewall of the gate electrode between the gate electrode and the drain region;
a lightly doped drain (LDD) region formed below the gate dielectric layer to overlap a portion of the gate dielectric layer and a portion of the first dielectric pattern; and
a gate silicide layer formed between the first dielectric pattern and the spacer,
wherein the source region and the body region have different conductivity types.
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