| CPC H10D 30/797 (2025.01) [H01L 23/5286 (2013.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 64/01 (2025.01); H10D 64/258 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0172 (2025.01); H10D 84/0186 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01)] | 20 Claims |
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1. A device comprising:
a first interconnect structure;
a second interconnect structure;
a stacked complementary transistor structure disposed between the first and second interconnect structures, wherein the stacked complementary transistor structure comprises a first transistor of a first type, and a second transistor of a second type which is opposite the first type;
a first contact connecting a first source/drain element of the first transistor to the first interconnect structure; and
a second contact connecting a first source/drain element of the second transistor to the second interconnect structure;
wherein the first and second contacts are disposed in alignment with each other; and
wherein the first source/drain element of the second transistor comprises an extended portion which extends beyond a gate of the second transistor towards the second interconnect structure.
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