| CPC H10D 30/797 (2025.01) [H01L 21/02532 (2013.01); H01L 21/0259 (2013.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/021 (2025.01); H10D 62/118 (2025.01); H10D 62/832 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01)] | 20 Claims |
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1. A semiconductor device, comprising:
a plurality of channel members disposed over a substrate and extending lengthwise along a first direction, each of the plurality of channel members comprising a rounded end when viewed along a second direction perpendicular to the first direction;
a plurality of inner spacer features interleaving the plurality of channel members;
a gate structure wrapping around each of the plurality of channel members;
a source/drain feature comprising:
a first epitaxial layer in contact with the substrate and the rounded ends of the plurality of channel members,
a second epitaxial layer in contact with the first epitaxial layer and at least one of the plurality of inner spacer features, and
a third epitaxial layer disposed over the second epitaxial layer; and
a dielectric etch stop layer disposed over and interfacing the third epitaxial layer,
wherein the plurality of channel members and the rounded ends of the plurality of channel members share a same composition,
wherein the first epitaxial layer, the second epitaxial layer and the third epitaxial layer comprise silicon germanium,
wherein a germanium content of the second epitaxial layer is greater than a germanium content of the first epitaxial layer,
wherein the second epitaxial layer and the third epitaxial layer are doped with boron (B),
wherein a boron doping concentration of the second epitaxial layer is greater than a boron doping concentration of the third epitaxial layer.
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