CPC H10D 30/6729 (2025.01) [H10D 30/6211 (2025.01); H10D 30/6219 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 62/151 (2025.01); H10D 64/01 (2025.01)] | 18 Claims |
1. A semiconductor device comprising:
a substrate;
an active pattern that extends in a first direction, on the substrate;
a plurality of gate structures on the active pattern, each gate structure including a gate electrode that crosses the active pattern and extends in a second direction that intersects in the first direction, and each gate structure including a gate capping pattern on the gate electrode thereof;
a source/drain pattern on the active pattern and between two adjacent gate structures;
a lower active contact on and connected to the source/drain pattern;
a silicide film between the lower active contact and the source/drain pattern;
a trench that is on the silicide film and the lower active contact and exposes the lower active contact, wherein a width of a bottom surface of the trench in the first direction is greater than a width of an upper surface of the lower active contact in the first direction;
an etching stop film along the bottom surface and side walls of the trench; and
an upper active contact that extends through the etching stop film, is in the trench, and is connected to the lower active contact,
wherein an uppermost surface of the etching stop film is coplanar with an uppermost surface of the upper active contact.
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