| CPC H10B 63/80 (2023.02) [H10B 53/30 (2023.02); H10B 61/22 (2023.02); H10B 63/30 (2023.02); H10N 50/01 (2023.02); H10N 70/011 (2023.02)] | 20 Claims |
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1. A semiconductor structure, comprising:
a substrate, having a first surface;
a plurality of transistors, located on the first surface and arranged based on a first preset pattern;
a plurality of transistor contact structures, corresponding to the transistors in a one-to-one manner, wherein bottom portions of the transistor contact structures are in contact with the transistors respectively, the bottom portions of the transistor contact structures are arranged based on the first preset pattern, and top portions of the transistor contact structures are arranged based on the shape of a regular hexagon;
a plurality of memory cells, corresponding to the transistor contact structures in a one-to-one manner, wherein bottom portions of the memory cells are in contact with the top portions of the transistor contact structures respectively, and the memory cells are arranged based on the shape of a regular hexagon and located at vertex positions and a central position of the regular hexagon; and
a plurality of memory contact structures, corresponding to the memory cells in a one-to-one manner, wherein bottom portions of the memory contact structures are in contact with top portions of the memory cells respectively, the bottom portions of the memory contact structures are arranged based on the shape of a regular hexagon, top portions of the memory contact structures are arranged based on a second preset pattern, and the second preset pattern is different from the first preset pattern;
wherein the bottom portion of the transistor contact structure is arranged opposite to the top portion of the transistor contact structure, and the bottom portion of the memory contact structure is arranged opposite to the top portion of the memory contact structure.
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