| CPC H10B 61/22 (2023.02) [H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10N 50/80 (2023.02); H10N 50/85 (2023.02)] | 20 Claims |
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1. A method for manufacturing a magnetic memory device, the method comprising:
preparing a substrate including a cell region and a peripheral circuit region;
forming a first lower contact plug on the cell region and peripheral conductive patterns on the peripheral circuit region;
forming a lower interlayer insulating layer on the first lower contact plug and the peripheral conductive patterns;
forming a second lower contact plug that penetrates the lower interlayer insulating layer on the first lower contact plug;
forming a data storage structure on the second lower contact plug;
forming an upper interlayer insulating layer covering top and side surfaces of the data storage structure on the cell region and covering the lower interlayer insulating layer on the peripheral circuit region, wherein a thickness of the upper interlayer insulating layer on the peripheral circuit region is formed thinner than that on the cell region; and
forming a through-hole and an insulating pattern on the peripheral circuit region, the through-hole including contact holes exposing top surfaces of each of the peripheral conductive patterns through at least the lower interlayer insulating layer, and a peripheral trench located on the contact holes and commonly connected to the contact holes,
wherein the insulating pattern is located between the contact holes,
wherein the data storage structure includes
a lower electrode,
an upper electrode on the lower electrode, and
a magnetic tunnel junction pattern between the lower electrode and the upper electrode, and
wherein a ratio of a height of each of the contact holes to a width of each of the contact holes adjacent to the top surface of the peripheral conductive patterns is equal to or less than 1.5:1.
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