US 12,279,437 B2
MRAM memory cell layout for minimizing bitcell area
Harry-Hak-Lay Chuang, Hsinchu (TW); Wen-Chun You, Hsinchu (TW); Hung Cho Wang, Hsinchu (TW); and Yen-Yu Shih, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 31, 2023, as Appl. No. 18/362,817.
Application 17/562,949 is a division of application No. 16/893,010, filed on Jun. 4, 2020, granted, now 11,244,983, issued on Feb. 8, 2022.
Application 18/362,817 is a continuation of application No. 17/562,949, filed on Dec. 27, 2021, granted, now 11,800,724.
Claims priority of provisional application 62/866,361, filed on Jun. 25, 2019.
Prior Publication US 2023/0380187 A1, Nov. 23, 2023
Int. Cl. H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/80 (2023.01)
CPC H10B 61/22 (2023.02) [H10N 50/01 (2023.02); H10N 50/80 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a substrate;
a transistor over the substrate and including:
a first source region;
a second source region;
a drain region between the first and second source regions;
at least one first channel region between the drain region and the first source region;
at least one second channel region between the drain region and the second source region;
a first gate structure overlying the at least one first channel region; and
a second gate structure overlying the at least one second channel region;
a first metal layer overlying the transistor;
a second metal layer overlying the first metal layer, wherein the second and first metal layers are configured to couple a common source line signal to the first and second source regions and to first neighboring first and second source regions of a first neighboring transistor of a first neighboring memory cell;
a magnetic tunnel junction, the magnetic tunnel junction including a lower ferromagnetic layer, an upper ferromagnetic layer and a tunnel barrier layer positioned between the lower ferromagnetic layer and the upper ferromagnetic layer, wherein the memory cell further comprises:
a fourth metal layer configured as a lower metal contact island coupled to the lower ferromagnetic layer and the drain region;
a fifth metal layer configured as an upper metal contact island coupled to the upper ferromagnetic layer; and
a sixth metal layer configured as a bit line and coupled to the fifth metal layer; and
wherein an x-pitch of the memory cell is a distance between the first source region and the second source region and includes a number of gate structures that is 2 or more.