US 12,279,436 B2
Non-volatile memory including negative capacitance blocking oxide layer, operating method of the same and manufacturing method of the same
Sanghun Jeon, Daejeon (KR); and Taeho Kim, Daejeon (KR)
Assigned to Korea Advanced Institute of Science and Technology, Daejeon (KR)
Filed by Korea Advanced Institute of Science and Technology, Daejeon (KR)
Filed on May 15, 2023, as Appl. No. 18/197,189.
Claims priority of application No. 10-2022-0059004 (KR), filed on May 13, 2022.
Prior Publication US 2023/0413574 A1, Dec. 21, 2023
Int. Cl. H10B 51/30 (2023.01); G11C 11/22 (2006.01); H10B 51/20 (2023.01)
CPC H10B 51/30 (2023.02) [G11C 11/223 (2013.01); G11C 11/2275 (2013.01); H10B 51/20 (2023.02)] 14 Claims
OG exemplary drawing
 
1. A non-volatile memory comprising:
a tunneling oxide layer formed on a channel;
a charge storage layer formed on one surface of the tunneling oxide layer;
a negative capacitance blocking oxide layer in which a dielectric layer and an imprinted polarization layer are sequentially configured on one surface of the charge storage layer; and
a gate formed on one surface of the negative capacitance blocking oxide layer;
wherein the imprinted polarization layer has a negative capacitance by a depolarization field induced as an initially aligned polarization is switched in response to a positive voltage being applied to the gate, the depolarization field being in a direction opposite to that of an electric field of the switched polarization.